I Would like to thank all the people who have bombarded me with interesting stuff and questions about I2C. I am also happy that my little knowledge could help.

Vincent September 1st 2000.
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I hope that those of you who know of interesting items for this FAQ will share with everyone. A good amount of stuff is turning up thanks to everyone's help. If you have a website you can put the FAQ or a link to the FAQ online there.
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The copyright does not limit the use of this FAQ for noncommercial purposes. I hereby give my permission to one and all to pass this FAQ around and post it wherever you want - as long as it is not for financial gain.

You are allowed to distribute portions of the FAQ as long as you incorporate the following note. 'Taken from The I2C FAQ' and provide a link to its storage on the internet.
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Normal Computer systems use ByteWide buses to accomplish this task. This results in lots of copper tracks on PCB's to route the Address and datalines. Not to mention a bunch of address decoders and glue logic to connect everything.

In mass production items such as TV-sets, VCR's and audio equipment this is not acceptable. Complex circuits often need multilayer boards, and these are simply too expensive for household goods. Furthermore lots of control lines implies that the systems is more susceptible to disturbances by EMC and ESD.The research done by Philips Labs in Eindhoven (The Netherlands) resulted in a 2 wire communication bus called the I2C bus.

I2C is an acronym for Inter-IC bus. Its name literally explains its purpose: to provide a communication link between Integrated Circuits.

Nowadays the extent of the bus goes much further than Audio and Video equipment.The bus is generally accepted in industry. Offsprings like D2B and ACCESS have made an attempt to find their ways into computer peripherals like keyboards, mice, printers, monitors, etc... . However they have been successed by the USB bus. Amazingly the USB bus steals some technology frmo I2C. The basic communication idea and adressing scheme is based on I2C.

The I2C BUS has been adopted by several leading chip manufacturers like Xicor, SGS-Thomson, Siemens, Intel, TI, Maxim, Atmel, Analog Devices.
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Every component hooked up to the bus has its own unique address whether it is a CPU, LCD driver, memory, or complex function chip.Each of these  chips can act as a receiver and / or transmitter depending on its functionality. Obviously an LCD driver is only a receiver ,while a  memory or I/O chip can both be transmitter and receiver.  Furthermore there may be one or more BUS MASTER's.

The BUS MASTER is the chip issuing the commands on the BUS.  In the I2C protocol specification it is stated that the IC that  initiates a data transfer on the bus is considered the BUS MASTER.  At that time all the others are regarded to as the BUS slaves.

As mentioned before, the IC bus is a Multi-MASTER BUS. This means  that more than one IC capable of initiating data transfer can be  connected to it. As MASTERs are generally microcomputers let's take a  look at a general 'inter-IC chat' on the bus.

Lets consider the following setup :

Case :  The CPU wants to talk to one of the attached components.

The CPU will issue a START condition  (see further on for description of all these conditions).  This acts as an 'ATTENTION' signal to all of the connected  ic's. ALL IC's on the bus will listen to the bus for incoming data.

Then the CPU sends the address of the device he wants to address.This takes 8 clock pulses. At this moment in time all  IC's will compare this address with their own.If it doesn't  match they simply do nothing and wait until the bus is released  by the STOP condition.If the address matches however the chip will produce a responce on the ACKNOWLEDGE signal of the CPU.

The ACKNOWLEDGE signal is issued by the CPU.When the chip whose  address matches sees the ACKNOWLEDGE on the bus it Pulls the  data line LOW. This is an indication to the CPU that there is  a chip with the wanted address on the bus.

Now the CPU can start transmitting or receiving data  In our case the CPU will transmit data.When all is done the  CPU will issue a STOP condition. This is a signal that the bus  has been released and that the IC's may expect another  transmission to start any moment.

We have had several states on the BUS right now :  START, address ,ACKNOWLEDGE ,DATA ,STOP. These are all unique conditions on the BUS. Before we take a closer look into these I will talk about the hardware of the BUS. This is necessary to understand what is physically going on.
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What i mean here is that you cannot set a voltage on the HIGH Level. It depends on the supply voltage of the connected IC's.However as this is mostly 5 Volts you can say that HIGH is 5 volts and LOW 0 volt. Nowadays the 3.3 volt ic's are emerging rapidly. It's clear that in this case the high level will be 3.3 volts. The latest revision of I2C provides a means of interfacing mixed voltage circuits.

The nice thing about this concept is that it has a 'built-in' bus mastering technique. If the bus is 'occupied' by a chip that is sending a 0 then all other chips loose their comm's capability. More will be explained about this further on in the Faq.

However the open collector technique has a drawback too. If you have a long bus this will have a serious effect on the speed you can obtain .  The higher this RC constant the slower you can go. This is due to the effect that it influences the 'sharpness' of the edges on the I2C bus . At a certain point the chip will not be able to distinguisch clearly between a logic 1 and 0.

Long lines present a capacitive load onto the output .Since the pull-up is passive you are facing an RC constant which will reflect onto the shapes of the signals.

What's more is that you can get reflections at high speed .This can be so bad that 'ghost signals' disturb your transmission and corrupt the data you transmit. And then even the Schmitt trigger at the input of the chip will not keep you out of trouble. The following image shows you exactly what can happen.

Therefore some strict electrical specs have been set forth. These are explained further on.

To overcome this problem , Philips has developed an Active I2C terminator. This consists of twin charge pumps. You can look at this device as a dynamic resistor. The moment the state changes it provides a large current (low dynamic resistance) to the bus. Doing this it can charge the parasitic capacitor very quickly. Once the voltage has risen above a certain level the high current mode cuts out and the output current drops sharply.

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A STOP condition is just the mirror of the above.

The Bus MASTER first releases the SCL and then the SDA line.

The start condition acts as a signal to all connected IC's that something is about to be transmitted on the BUS. All the devices on the bus will go to listen mode and check the incoming data for a match against their address on the bus. The Stop condition  tells the connected chips that the message has been completed and that the bus is free to use.
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First the MASTER sets the data line to the appropriate level by pulling or not pulling the SDA line low. Then it releases the SCL line for some time and pulls it low again. Now it can change the state of the SDA to the level required for the next bit and the process continues all over again.

The DATA must stay valid during the HIGH level of the CLOCK pulse. If the data chenges while the clock line is high this will bee seen as either a START or STOP condition occurring ! ( depending on the direction of change ).

Using the above information ,a transfer could look like this :

As you can see in the above it is not necessary to have a clock with a constant duty cycle.The BUS is very relaxed even in such a way that you can stop the clock in the middle of a transaction and then continue later on. This is very useful. Consider the following :

Your cpu is in the middle of a transaction and gets an interrupt. It can process the interrupt first and continue its message later on without any problem. (try doing that on RS232 !). Since there is no minimum clock speed set you can have the communication running at whatever speed you can handle.
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Concerning the SLAVE pulling low the SDA line it is so that generally the addressed IC will already have pulled the SDA line low even before the MASTER has set the clock HIGH. It is the falling edge of the last clockpulse that triggers the slave.

In the real life it is good practice to actually look during the high level of the CLOCK if the SDA is being pulled LOW or is LOW. Some chips need some time to process the address before they can respond by pulling the SDA low. This can be the fact when the addressed SLAVE is another CPU or an EEprom. Suppose the following : You address a SLAVE CPU. But just before the SLAVE CPU can pull the SDA low it has to process some interrupt occuring.If the transfer issuing CPU would look to the SDA line immediately it would see a HIGH level. Thus it would look like the SLAVE is not responding. The Same goes for EEproms. Since storing data to EEprom cells takes some time the ACKNOWLEDGE is used to indicate that the programming has been completed. So after the last bit has been transferred the EEprom starts writing the received data into its array. It leaves the SDA line in the LOW state until this action has been completed. this means that after the ACQ clockpulse the slave keeps the SDA line LOW !. It is the task of the masdter to wait now until SDA becomes high before continuing. this process might seem to violate the I2C bus spec but actually it doesn't. This process is called synchronisation. ( see the topic explaining this process ).

I have once spend a whole day figuering this one out !.The system once in a while did not work like it should have because the addressed device was not capable of generating an ACKNOWLEDGE in time.

The best way to do an ACKNOWLEDGE , in my humble opinion,is like this: Put the SCL high, wait some time (your TIMEOUT value), then check if SDA is LOW. If it is LOW - > The chip is there. If it is HIGH -> The chip isn't there. When removing the ACQ clockpulse check if the SDA line effectively goes high. If not : the chip is in process of writing internally.

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I figuered out in real life that on the last transmitted byte you do not have to wait for the ACKNOWLEDGE. You can directly issue a STOP command. Apparently there are some chips that do not generate an ACKNOWLEDGE here !. Theoretically they should generate an ACKNOWLEDGE but for some reason they don't. The best way is as follows : after you have transferred your last byte just to set the SCL high , wait some time , take it low and then issue a STOP command. There is an exception though.

When all 8 bits have been read the MASTER must GIVE the ACKNOWLEDGE or to the SLAVE  or stop the transmission.

To give an acknowledge to a slave the master holds the SDA line low and gives a clockpulse on SCL. To stop stransmission you simply issue a stop condition on the bus : Keep SCL and SDA low. Now make SCL high , and then make SDA high.

If you give an ACQ pulse to the slave you have to read another byte. Immediately after the ACQ the slave will take hold of the SDA line and you might no longer be able to give a stop before clocking out the next 8 bits.

Note: Here the FAQ has been greatly modified. In the previous FAQ the text caused a lot of confusion.

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Thats an easy one. This is beeing determined by the SLAVE address.  Each byte consists of 8 bits. The 8th bit in the SLAVE address has a  special meaning. When it is set to 0 it means you want to write to  your SLAVE. When it is set to 1 it means that you you want to READ.  You could see this as follow. The Even addresses are WRITE addresses, the ODD addresses are READ addresses. Each device has a consecutive WRITE and READ address.

Now you can even go one step further and generate another START and then address the SLAVE as write. Send a new Data byte (which acts on  the location pointer), send another start, enter read mode etc ......  This combined mode is really a very flexible means of addressing complex components. This may look very messy. But it has its pro's and con's:

PRO: If you have 2 CPU's on your bus which could want to take the bus this will assure you that you will be able to continue your  actions on the bus without interference from the other CPU. Remember that when you have generated a START and have sent the SLAVE address the other CPU too will be waiting until a STOP appears on the bus. So he will not try to put something on the  bus.There could be a risk involved using normal READ and WRITE operations

Picture this situation : CPU 1 accesses the MEMORY and sets the location pointer to 84 and issues a STOP condition. Now the BUS is FREE. CPU 2 sees this and thinks : okay my turn. He sets the location pointer to 92 because he wants to do something at that location. Now the bus is free again. CPU 1 says : aha ! the bus is free. Time to write for me. Now the data will land on location 92 and not on location 84 as it should have been. So : If you are dealing with memories on a Multimaster bus always use this last method.  It keeps you out of trouble.

CON:  If you have lots of operations to do you can create a bottleneck situation. The other CPU could be waiting and waiting for a  chance to have his turn on the bus.

But is you don't have a MultiMaster environment this all is not necessary.

Congratulations you have reached the EXPERT grade.  :-)
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When CPU 1 issues a START and sends an address the other one will back  off. Because of the fact that if the address does not match his own  address he has to wait until the bus is free. (STOP condition). So far  no problem. But as Murphy is, as usual ,always around. It's when you least expect it that it goes wrong.Fortunately the BUS setup helps us out here.

When you (as a MASTER ) change the state of a line to HIGH , you MUST always check that it has gone to the HIGH level. If it hasn't : BACKOFF ! it's occupied !. Wait for a STOP to occurr and then retry.

What could happen is that the TWO CPU's start communication on the  same moment in time.Since it is an open collector/drain bus they can  only PULL the line low. They cannot force it HIGH. (they can only  leave it HIGH by not turning on their output transistor).

So they start transmitting. And all goes well as long as they both are  asserting the same levels. (during START it's okay.They are doing the  same) Then they start transmitting data. for the first couple of bits all goes well until suddenly diaster strikes. Bit 3 is different !. CPU1 wants to send a 0 while CPU2 wants to send a 1.

Now CPU 1 has pulled SDA LOW. CPU 2 leaves SDA open. Remeber that you cannot force the Line HIGH It is the job of the pull-up resistor to do that.  Since they are both running clean and good written code they are  testing what they have put on the BUS. CPU 1 sees that he has written a 0 and says 'okay for me'.. CPU 2 on the other hand sees that the line is LOW  while he has left it HIGH ! so he knows that by now someone else has taken control. Time to  BACK OFF !.

Now in an ideal world CPU2 would do even more !. When he knows for sure that this is the first byte after the START generation he will switch from tranmist to receive mode !. Why ? Well simple: CPU1 might be trying to talk to CPU2 !
If this is the first byte after a START condition this means that it is effectively a slave address beeing transmitted. CPU2 has to check that this slave address beeing put on the bus is not his own. If it is not his address he has to wait for the STOP command to appear on the bus before attempting to take control again. On the other hand. If the address is his own address he must respond. In the  latter case CPU2 becomes the slave device on the bus. This way all ends up well.

So from the above story we can conclude that is the one that has its  line LOW that always wins. The One wich wanted the line to be HIGH when  it is beeing pulled low by the other looses the BUS.We call this a 'loss of arbitration' or BACK-OFF. When a BACKOFF situation is generated it is good practice to have the cpu, that has to BACKOFF, wait for a STOP condition to appear on the bus.The other one is still busy transmitting.

The above example showed a situation where the two CPU's were in perfect sync with each other. In most situations this will not be the case. But even then the arbitration will still work. Suppose one of the CPU's missed the START condition and still thinks nothing is going on ... , or it came just out of reset and wants to start talking on the bus. These are real-life cases that WILL happen in a mulitmaster environment. ( remember Murphy's Law !) . Consider a multimaster system that has just been powered up. You will not know which cpu will come out of  reset first.

So actually this mechanism does not only do arbitration , it is also very effective at ensuring that the information beeing sent is not lost or corrupted !. The message from the winning CPU is not distorted in any way.

If you struggled trough all of this , and the previous chapters then you are ready to face the world of MultiMaster I2C
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When a slower slave is attached to the bus then problems may rise. Suppose the following : The master reads a byte from a slave. Lets say an A/D convertor. The slave needs some time to make a conversion. The master adresses the slave in read mode
--------------------...
|S|READ_ADRESS|WACK|...
--------------------...
In the Wait_for_ack module happens something worth looking at.

In a normal ACQ sequence the slave will pull the ACQ line low immediately after the 8th clock pulse and before the ACQ clockpulse. The master will send a clockpulse , and sample the SDA line during this pulse. If SDA is low it means that the slave aknowledges the information sent. When the ACQ clockpulse is removed the slave releases the SDA line.

Now lets suppose that the slave has detected his home adress. It starts a conversion and waits until this conversion is done before giving acknowledge.That way the master can read the result immediately after the Acknowledge sequence. Of course the master would have timed out and considered the slave not to be present on the bus.

Now the synchronisation meachanism can come in handy. The Slave can pull the SCL low as long as needed. The master is then not able of giving the ACK clockpulse because it cannot  raise the SCL line.Of course the master software must check this state. This is the routine the master must execute for a synchronisation aware Wait_for_ack sequence

What happens is this : (in our theoretical model)

The master has sent the last bit of the slave adress on the bus. The slave recognises its adress and pulls the SDA line low.  ( it wants to acknowledge because it has detected its adress ).  At the same time it starts the A to D conversion and pulls the SCL line low.

The master now wants to start the Wait_for_ack sequence. So it makes SDA high.( Never minding the Slave holding it low )

Now the master releases the SCL line.When testing the level of the SCL line the master will see that it is still low.This is due to the fact that the slave is holding the SCL low.So the master enters a loop that runs until the SCL line effectively turns high. The moment the slave has completed the conversion it releases the SCL line.

The master detects that the SCL has become high and checks the SDa line. Since the slave turned it low long ago it sees a valid acknowledge. The master will now begin to read the result of the conversion.

This technique is used by the serial EEproms on I2C. There are a number of drawbacks involved when implementing this.  If the bus gets stuck due to an electrical failure of a circuit the master can go into deadlock.Of course this can be handled by timeout counters.

Another drawback is speed.The BUS is locked at that moment. If you have rather long delays (long conversion time in our example above) then this  penalizes the total bus speed a lot.

  address  R/W
  0000 000 0  : general call
                address
  0000 000 1  : start byte
  0000 001 x  : CBUS address
  0000 010 x  : address
                reserved for
                different bus
                format.
  0000 011 x  !
  0000 100 x  !
  0000 101 x  !} to be defined
  0000 110 x  !
  0000 111 x  !
 

This implements that all addresses below 16 are reserved for special  purposes. The reason behind this is that there are other buses around. Using this scheme you can connect device that uses a different bus to the I2C bus !. It is possible to put SPI, I2C, uWIRE and CBUS devices on the same I/O pins of your CPU. Since all buses different to I2C use 3 lines you can
cut down on you CPU pin load.

In the FAST mode the physical bus parameters are not altered. The protocol,Bus levels,Capacitive load etc.. remain unchanged. However the datarate has been increased to 400 Kbit/s. To accomplisch this task a number of changes have been made to timing.

Since all CBUS activities have been canceled ,there is no compatibility anymore with CBUS timing.The development of IC with CBUS interface has been stopped. The existing CBUS ic's are being taken out of production.

The input of the FAST mode devices all include Schmitt triggers to suppress noise. The output buffers include slope control of the falling edges of the SDA and SCL signals.If the power supply of a FAST mode device is switched off the BUS pins must be floating so that they do not obstruct the bus.

The pullup resitor must be adapted. For loads up to 200 pf a resistor is sufficient.For loads between 200pf and 400pF a current source is preferred.

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A chip that conforms to the new standard receives 2 address bytes. The first consists of 5 * a ONE ,the 2MSB's of the address and the Read/Write bit. The second byte contains the LSB's of the address.
-----------------------
|S|11111A9A8 R/W|WA|...
-----------------------
-----------------------
A7A6A5A4A3A2A1A0|WA|...
-----------------------
This scheme insures that the 0 bit addressing mode stays completely transparent for the other devices on the bus. Normally any new design should adept to this new addressing scheme.
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This depends on the load of the bus and the speed you run it at. In typical applications a few meters (3 to 4). Better: The maximum capacitive load has been specified (electrical Spec's in this FAQ).

If you run at a lower clock frequency then you could go further. If you are careful in routing your PCB's and cabling then you can take it further.I once had an application that had a total of about 100 meter cable in it. The entire system was clocked on something like 500 Hz. I used twisted pair cable and twisted SCL with GND and SDA with VCC. No problem.The systems is now up and running for over 5 years.

If you need to go far at high speed then you can use an active current source . Philips has a standalone product for this purpose. Or you could build one yourself. Another thing to be taken into account is the amount of noise picked up by long cabling. This
noise can disturb the signal transmitted over the bus so badly that it becomes unreadable.

A last thing to be taken care of is the bus termination. Long lines will cause refelections. These reflections can cause 'ghost signals' to appear.This kan be overcome by using a charge pump mechanism like the Philips device has. See also next topic.

I want to extend it ''by the book''. Is there something like a Buffer  for I2C ?

Yes indeed this exists. Philips manufactures a special chip to buffer the bidirectional lines of the I2C bus. Typically this is a current amplifier. What it does is force current into the wiring  (a couple of mA). That way you can overcome the capacitance of long  wiring. Philips P87B715

However You will need this component on oth sides of the line.The charge pump in this devices can deliver currents up to 30mA. And that is way too much for a normal I2C chip to handle.With these buffers you can handle loads up to 2nF. The charge amplifier 'transforms' down this load to a 200pF load which is still acceptable by I2C components. Another possibility is to make such a charge pump yourself. This is fairly easy and can be accomplished by 1 chip and a few resistors. See a bit further on for details.

Can i isolate an I2C bus ? (using optocoupler or whatever)

This is possible. The circuit is rather complex due to the bidirectional nature of the I2C BUS. Actually there are a number of solutions here. One has appeared in electronic design new , one is included in the elektor book on i2c and yet another one has been published in an issue of Elektor. See the end of this FAQ for information on these books.
However : Here it comes (for once channel).

Component Values

1: 270 Ohm
2: 3300 Ohm
3: 1800 Ohm
4: 1000 Ohm
5: PNP like 2n2219 or BC557
6: NPN like 2n2222 or BC 547
Optocouplers : 6n139 , 4n27 or Til 111

A couple of remarks. Since the speed of the I2C bus can be rather high it is reommended to use a fast optocoupler.However this circuit will not work on speeds higher then 10KHz.A 6N139 will do the job in all cases. The 2 PNP and 2 NPN transistors can be any standard type. Like 2N2219 and 2N2222 (USA) or BC547 and BC557 (EUROPE).

How does it work ?
The problem with bidirectional lines is that a buffer tends to get stuck on a certain level. In the above schematic this has been dealth with. In the following explanation we assume that the left side is transmitting and the right side is receiving.Since the circuit is symmetrical you could do it the other way around too. Suppose you send a logic 1 into the left side. The Led of the top optocoupler will stay dark. Since its transistor does not receive any light it is not turned on. The next transistor does not get driven and the line at the end is beeing pulled high via resistors 1' and 3' . The PNP transistor 5' will not get driven. So the Led connected to it will not light. So there is no feedback signal . So far so good.

Now lets look what will happen if we send a 0. The first transistor 5 will be turned on. Thus the led connected to it will start emitting light.This results in the fact that it's matching transistor will turn on . The transistor connected to the Emittor of will be turned on too. The output line is now beeing pulled low via resistor 3' . This low level would turn on the PNP transistor. This would result in The other optocoupler to light , it's transistor to turn on etc etc .. The circuit would go into a lock-up.
But since the NPN transistor is pulling the Anode of the led to ground this will not happen. In this way we have eliminated the deadlock.

What if i don't want to emulate the bus by software or if i don't have an I2C interface on my system ? Is there something like an I2C controller ?

Yes indeed. There is a special chip to do the I2C interfacing. The PCD8584 or PCF8584 incorporate a complete I2C interface. These chips are designed in such way that they can interface to almost any microcontroller or computer around.

I am puzzled on how to generate a repeated start condition.

I make the SCK high and my device pulls SDA low to acknowledge. So far no problem but how do i make a new start now ?. The device is pulling SDA low. !

First you have to complete you ACK cycle. To do this you must make SCL low again. The slave will release the dataline when it detects that SCL went  logic low.  Now you can issue a stop command. To do this you make the SCK  high again and then pull low the SDA line.  This is the confusing part of the procedure. Normally one would  suspect that by making the clock high again you will be clocking  in the first bit of a new byte. As a matter of fact that is the case.  But since the chip will detect a START condition this operation gets  cancelled.

Is it okay to abort an on-going transmission any time.

According to the specification this !should! work. It depends on the layout of the component. A real I2C compatible  ic will be able to handle this. You should test this before you  use it.
Normally when a START or STOP condition is detected the internal logic of the chip is forced into a certain state. Internally the part that detects START and STOP is differnet then the logic that does all other processing. The START together with the address register is to be considered as a functional unit inside the chip.

When a START is detected all internal operations are cancelled and the chip will compare the incoming data with its own address. When a STOP is detected ALL chip's on the bus will reset their  internal logic to IDLE mode. This is also used to cut power consumption. When a STOP is detected all logic is shut down except for the START detector. When a start is issued on the bus the START detector will 'wake-up' the rest of the internal logic.

Do i need to give the ack in read mode on the last byte.
 My chip starts sending data and occupies the bus ... .

This is a question that got me puzzled .Indeed this is a bit strange. Normally if you have read the last byte in a chip and generate an ACK  the chip should do nothing anymore. So the bus is clear for you to create a STOp condition. Apparently there are some chips that start transmitting data again.

Digging in to to spec showed an error in my FAQ. On the Last byte READ you must generate a NACK (NOT Acknowledge).  Check out the description of the READ mode

I read the SDA and SCL are bidirectional.Why does the clock line  need to be bidirectional ?

The clock line needs to be directional when using a MULTIMASTER protocol and when using synchronisation protocol. When you are using only one Master then this is not required since the clock will always be generated by the Master and you only  have one on the BUS. If you run Multimaster then this changes.The Master must be able to receive data from the other master. At that time it must be able to check the Clock line too. For more information about bus synchronisation check out the topic dedicated to it.

Can i monitor an I2C bus in some way ?

This is possible. There are a few commercial I2C monitor / debuggers around that can do this.Information on these cards can be found elsewhere in this Faq There is another possibility to do this. By using the PCF 8584 chip from philips. This is a universal CPU to I2C interface. This chip has a certain mode in which it takes not part in the real I2C action but unly records what is going on. It listens to all adresses but does not generate an acknowledge.Using some software routines and a small cpu you could make a universal I2C data logger.

Is there a way to test/debug I2C buses ?

There is no general way to Debug an I2C bus. However a few guidelines might help to get it running.
First thing is to check the levels on the bus. You should see a clear signal that has a low level that is lower then 0.8 volt and a high level which is at least 3.5 volts. ( assuming you are running in a 5 volt environment )

If the high level is not high enough or does not rise fast enough then you can try to lower the value of the pull up resistor. You must take care however not to surpass the maximum allowable current in the I2C driver stage . The minimum allowable resistor for a 5 volt drive I2C bus is 5volts / 3mA = 1600 Ohms. A typical value of 4700 ohm should do fine.

Make sure the bus is not 'stuck' . This could be the result of a bad power supply (chips go into latch up during power-on) or a bad chip .
also check the Troubleshooting section

I want to experiment with I2C .Are there demokits available.?

Philips has at least 1 board ( i know of two different boards) for these purposes. It features a bunch of different I2C devices such as EEprom ,digital I/O ,A/D D/A , controllable switch , Real time clock , Ram , Display driver (led and LCD with even an alphanumeric LCD) and also can host a number of their 8051 compatible CPU's.

For people wanting to control I2C from their pc they can either buy a card or build one themselfves. A number of Programs is available to control I2C devices from this interfaces. You can use the Philips / signetics software or use the driver i wrote to control the I2C bus from within your programs.

Are there plug in board available for IBM Pc to emulate I2C ?

There are a number of debugging tools out there which can monitor an I2C bus .
Philips has one of these tools available. Contact you Philips/Signetics representative for more information.
I2C Bus monitor MIIC-101

Micro Computer Control Corporation
PO Box 275
17 Model Ave
Hopewell New Jersey 08525
USA

Calibre ICA-90 I2C Adapter as IBM PC Plug-in Board
Calibre electronics Ltd
Broomfield House
Bolling Road
Bradford BD4 7BG
England
Also available from Farnell Components  Part no : 256-109 cost : approx 350 Us $

In USA you can also contact

Saelig Co.
1193 Moseley Rd
Victor New York 14564

I have problems with long buses. Can i make an active pull-up ?

Absolutely. If you need to go off board however then you should use the P87B715 device from philips.
for on board you can use following solution. Here comes the Schematic:

Now how does it work ?

First of all Rs. This is a series resistor used to minimize cross talk and undershoot .It also protects the I/O drivers of the I2C devices against overvoltages and overcurrent injection. These resistors are advised if you run a long bus on high speed ( such as in enhanced I2C mode). When the bus becomes free all output stages on the bus are turned off and SCL (or SDa for that matter) become high. This will not happen immediately , but the voltage will rise during a certain time. Now Suppose the switch is not there. The charge time of the bus capacitor is determined by the value of R1 only . The higher one of them is the longer it will take for the bus to reach a sufficient stable High level. We can't make the Series resistor too small because then we will go out of spec on the maximum allowable current into one I2C device when it turn's it's output driver on.

When we calculate for a current of 3ma we end up at approx 1800 ohms for the series resistance. 5volts / 3ma = 1666 Ohms .
To stay somewhere below this 3mA rating we take 1800 Ohms.The charge time for a bus capacitance of about 200pf would be around 360 nS. That is out of spec.The Spec for rise or fall time in Fast I2C is set to approx 300nS.
But we can't drop the value of our resistor without breaking the other spec of 3ma Max current.
Now if we had a means to change the value of the resistor temporarily.... And that's exactly what is done with the Analog Switch. If the voltage level sensed by the switch is in the range 0.8 to 2 volts then it will turn on. Meaning that the moment the voltage on the SDa line starts rising , this resistor will kick in and increase charge current to a value of 5volts/(1K8//1K2) =
720 Ohms. the charge current will then rise to 5 volts / 720 Ohms = 7 mA. This is allowable for a brief period of time. Of course all of this is a dynamic process. The actual charge current will change due to the fact that the bus voltage will rise.
A small graphical representation will explain more:

Wave 1 represents the turn off of the I2C device.So the bus must go to a logic 1
Wave 2 is the what you get if you only use a resistor. The bus 'slowly comes up to 5 volts due to the RC constant of Rpull-up and Cparasitic
Wave 3 shows the kicking in of the Analog switch. If the bus gets at approx 0.7 volts it kicks in and kicks out when the bus reaches approx 3 volts
Wave 4 is how the voltage on the bus changes. You can clearly see that it rises much faster when the switch is turned on.
And finally wave 5 show the current flowing into the I2C device. It starts at approx 3mA.

When the output stage is turned off this current slightly drops due to the fact that the voltage on the bus is rising. The moment our switch kick's in you see the current double. The same effect is then present as before the switch closed: the current drops as the bus voltage rises.When the switch opens again the current drops a little to charge the capacitor up to 5 volts. But at that time all chips already detect a logic one and are well withing the 300nS. Rise time.

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It is written in PseudoCode which is an imaginary programming language that any programmer should be capable of porting to his/her favorite language.

First we will define a set of basic interface routines. All text between / / is considered as remark. Following variables are used :

n,x = a general purpose BYTE
SIZE =  a byte holding the maximum number of transferred data at a time
DATA(SIZE) =  an array holding up to SIZE number of bytes. This will contain the data we want to transmit and will store the received data.
BUFFER =  a byte value holding immediate received or transmit data.